IPC@CHIP® RTOS-PPC – API Documentation
The following table lists the power save mode options available to control the amount of power consumed. The first column of the table specifies the number to be entered in the CHIP.INI POWERSAVE entry. The modes which cannot be selected from the CHIP.INI file are indicated not available (n/a).
The BiosPowerMode enumerator value passed to the BIOS_Power_Save() is shown in the second column.
No power saving. All devices are left operating at full power. This option provides no performance improvement over the default mode 1. It is offered only to allow users to make worst case power measurements during developement.
Enable dynamic power management. Functional units enter a low-power mode automatically if the unit is idle. This does not affect the operational performance and is transparent to software or any external hardware. (Note: Modes BPM_DOZE, BPM_NAP and BPM_SLEEP also enable this feature.)
Enter DOZE mode when ever system is idle. In DOZE mode, the CPU clock's Phase Lock Loop (PLL), time base, and snooping remain active. A snoop hit causes the CPU to enable the Data Cache, copy the data back to memory, disable the cache, and then return to the DOZE mode. An interrupt restores normal operation within a few CPU clock cycles.
Enter NAP mode when ever system is idle. In NAP mode, the CPU clock's PLL, time base and decrementer remain active. An interrupt restores normal operation within a few CPU clock cycles.
Enter SLEEP mode when ever system is idle. In SLEEP mode, the CPU clock's PLL remain active. The CPU's time base and decrementer are disabled in this mode. (The @CHIP-RTOS-PPC uses the decrementer for the task time-limit or task time-slicing options.) An interrupt restores normal operation within a few CPU clock cycles.
The system will be put to sleep, including peripheral devices. The CPU clock's PLL is stopped, as well as all system clocks except for that driving the RTC. The RTC continues to run and its alarm function is one of the mechanisms which can bring the system out of this deep sleep. Only a select group of hardware interrupts can awaken this sleep.