IPC@CHIP® RTOS-PPC – API Documentation

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void spiInit ( BYTE  idx,
unsigned int  mode,
unsigned int  div 
)

This function must be called to initialize the SPI master interface on the respective PSC group.

This API tests if the dedicated SPI bus on PSC3 can be used in conjunction with the current PSC3 group mode (UART, CODEC). If the SPI mode can not be used in conjuction to the current mode, e.g. when the PSC3 group is setup for GPIO usage, the PSC3 group will be set to SPI only mode.

Parameters:
idx SPI bus index
     0 = dedicated SPI on PSC3 or GPT
     1 = CODEC1 in SPI mode on PSC1
     2 = CODEC2 in SPI mode on PSC2
     3 = CODEC3 in SPI mode on PSC3
     6 = CODEC6 in SPI mode on PSC6

mode SPI mode bits
     Bit0-1: SPI mode
             0 = SPI_MODE0 => CPOL=0, CPHA=0
             1 = SPI_MODE1 => CPOL=0, CPHA=1
             2 = SPI_MODE2 => CPOL=1, CPHA=0
             3 = SPI_MODE3 => CPOL=1, CPHA=1
     Bit3: SS Autodrive mode
             1 = SS Autodrive mode enabled (SPI_AUTODRIVE)
             0 = SS Autodrive off, use spiSetSS() to set the SS signal
             Note: This option is only supported on the dedicated SPI bus (index 0).
             The CODEC SPI bus interfaces ALWAYS use the SS Autodrive mode.
     Bit9: Shift order
             1 = Shift LSB first (SPI_LSBFIRST)
             0 = Shift MSB first
     Bit10: Bidirectional mode
             1 = Bidirectional mode enabled, in this mode MISO is not used, MOSI becomes MOMI (SPI_BIDIRECTIONAL)
             0 = Normal mode
             Note: This option is only supported on the dedicated SPI bus (index 0).
     Bit11: SS mode
             1 = SS is held low for the number of transfered bytes (SPI_MULTIPLE_BYTES)
             0 = SS toggles with every transfered byte
             Note: This option is only supported on CODEC SPI busses (index 1-6).
     Bit12: PSC3/GPT
             1 = SPI on GPT (Timer2 - Timer5) (SPI_ON_GPT)
             0 = SPI on PCS3 (PCS3_6 - PSC_3_9)
             Note: This option is only supported on the dedicated SPI bus (index 0). This bit is only checked inside spiInit(), not inside spiReserveBus().

div SCK clock divider
     Bit0-2: SPR (see Formulas)
     Bit3: unused
     Bit4-6: SPPR (see Formulas)
     Bit7: unused
SS Delay After Transfer (The length of time that SS stays high/inactive between consecutive transfers.)
     Bit8-23: DTL (see Formulas)
     Note: This option is only supported on CODEC SPI busses (index 1-6).
SS to SCK Delay (The length of time the SPI master delays after SS goes low/active before the first SCK transition of the serial transfer.)
     Bit24-31: DSCKL (see Formulas)
     Note: This option is only supported on CODEC SPI busses (index 1-6).
Formulas:
                         IPB clock
SPI clock = -----------------------------
                 (SPPR+1) * 2(SPR+1)


                                 DSCKL + 1
SS to SCK Delay = -----------------------
                                 IPB clock


                                         DTL + 5
SS Delay After Transfer = -------------------
                                         IPB clock
Compatibility:
Please note that the interpretation of the div parameter and the SPI clock calculation formula has changed when compared with SC1x, SC2x and SC1x3 systems.
Returns:
Nothing
Since:
SC2x3 V1.00 - CLIB V1.00
Changes:
SC2x3 V1.02 - CLIB V1.02: Add SPI on GPT mode
See also:
spiSlaveInit(), SysPublic





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