IPC@CHIP® RTOS-PPC – API Documentation

Header image

Main page

void spiSlaveInit ( BYTE  idx,
unsigned int  mode 

This function must be called to initialize the SPI slave interface on the PSC3 group. If SPI can be used in conjunction with the current PSC3 group mode (UART, CODEC), it will, else the PSC3 group will be set to SPI only mode.

To use the SPI slave interface the user has to install an interrupt service routine for the SPI interrupt. An interrupt occurs after the eighth SCK cycle in a data transfer operation to indicate that the transfer is complete.

CPHA=0: If the SS line is not deasserted between the successive transmissions then the content of the SPI Data Register (written with spiSlaveWrite()) is not transmitted, instead the last received byte (spiSlaveRead()) is transmitted. If the SS line is deasserted for at least minimum idle time (half SCK cycle) between successive transmissions, then the content of the SPI Data Register is transmitted. Writing the SPI Data Register with spiSlaveWrite() is only allowed when SS is high.

CPHA=1: The SS line can remain active low between successive transfers (can be tied low at all times). Writing the SPI Data Register (with spiSlaveWrite()) is allowed after the last SCK edge (inside interrupt service routine).

idx SPI bus index
         0 = dedicated SPI on PSC3 or GPT

mode SPI mode bits
     Bit0-1: SPI mode
             0 = SPI_MODE0 => CPOL=0, CPHA=0
             1 = SPI_MODE1 => CPOL=0, CPHA=1
             2 = SPI_MODE2 => CPOL=1, CPHA=0
             3 = SPI_MODE3 => CPOL=1, CPHA=1

     Bit9: Shift order
             1 = Shift LSB first (SPI_LSBFIRST)
             0 = Shift MSB first

     Bit10: Bidirectional mode
             1 = Bidirectional mode enabled, in this mode MOSI is not used, MISO becomes SISO. (SPI_BIDIRECTIONAL)
             0 = Normal mode

     Bit12: PSC3/GPT
             1 = SPI on GPT (Timer2 - Timer5) (SPI_ON_GPT)
             0 = SPI on PCS3 (PCS3_6 - PSC_3_9)

     Bit13: Polling mode
             1 = SPI interrupt is not used, must use spiSlaveState() to poll the state (SPI_POLLING)
             0 = SPI interrupt is used, must install a ISR for SPI interrupt

     The remaining bits are reserved and should be set to 0 for future compatibility.
SC2x3 V1.00 - CLIB V1.00
SC2x3 V1.02 - CLIB V1.02: Add SPI on GPT mode, add polling mode
See also:

Top of page | Main page

Copyright © 2018 Beck IPC GmbH
Generated on Thu Nov 1 13:20:16 2018 by Doxygen 1.6.1