IPC@CHIP® RTOS-PPC – API Documentation

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static void cacheSync ( DWORD  start,
DWORD  stop 
) [inline, static]

This inline function performs a synchronization of the caches. This is important when the processor alters a memory location that may be contained in an instruction cache.

This function is necessary because the processor does not maintain instruction memory coherent with data memory. Software is responsible for enforcing coherency of instruction caches and data memory. Since instruction fetching may bypass the data cache, changes made to items in the data cache may not be reflected in memory until after the instruction fetch completes.

Parameters:
start Start address
stop Stop address
See also:
cacheStore()
Compatibility:
This function is not available in the SC1x, SC2x and SC1x3 C-Library.
Since:
SC2x3 V1.00 - CLIB V1.03





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