IPC@CHIP® RTOS-PPC – API Documentation

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FPU - "Floating-Point Unit" refers to the hardware within the CPU providing floating-point arithmetic. This includes 32 floating-point registers and a status register, FPSCR. The system does not permit the use of floating-point within Interrupt Service Routines. (To do so can damage the floating-point context of a task.)

MMU - Memory Management Unit refers to the hardware within the CPU which protects against illegal memory accesses. This hardware is used to restrict where application programs can read and write.

TLB - "Translation Lookaside Buffer" refers to some hardware registers used by the CPU's Memory Management Unit to speed up page address translation.

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