IPC@CHIP® RTOS-LNX – API Documentation

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Mutually exclusive pin configurations

This page describes the mutually exclusive pin configurations of the IPC@CHIP®. The following setups are currently possible:

SC1x5


SDIO interfaces

SDIO1
group
SDIO1GPIO, PWM, ADC, SPI1 slave
SD1_CLKSD1CLKPIO49 (Bank=1,Bit=17)
SD1_CMDSD1CMDPIO48 (Bank=1,Bit=16)
SD1_DATA0SD1D[0]PIO50 (Bank=1,Bit=18)
SD1_DATA1SD1D[1]PIO51 (Bank=1,Bit=19)
SD1_DATA2SD1D[2]PIO52 (Bank=1,Bit=20)
SD1_DATA3SD1D[3]PIO53 (Bank=1,Bit=21)
CSI_DATA05SD1CDPIO122 (Bank=3,Bit=26) / 0CS1
GPIO1_IO02SD1WPPIO2 (Bank=0,Bit=2) / AIN2
GPIO1_IO05SD1VSELPIO5 (Bank=0,Bit=5) / PWM4 / AIN5

SDIO2
group
SDIO2GPIO, PWM
NAND_RE_BSD2CLKPIO96 (Bank=3,Bit=0)
NAND_WE_BSD2CMDPIO97 (Bank=3,Bit=1)
NAND_DATA00SD2D[0]PIO98 (Bank=3,Bit=2)
NAND_DATA01SD2D[1]PIO99 (Bank=3,Bit=3)
NAND_DATA02SD2D[2]PIO100 (Bank=3,Bit=4)
NAND_DATA03SD2D[3]PIO101 (Bank=3,Bit=5)
NAND_ALESD2RESPIO106 (Bank=3,Bit=10) / PWM3

The SDIO interfaces are enabled by default. You can choose to disable them via the CHIP.INI entries SDIOx_ENABLE. In this case the pins of these interface groups can be used as GPIOs. Some of these pins have additional functions, like PWM or ADC. This pin functionality will be activated when the corresponding API function is called to initialize the interface, e.g. pwmEnable().


UART, I2C, SPI, CAN interfaces

UART1
group
UART1UART1 + RTS/CTSUART1 + RS485
UART1_TX_DATATXD1TXD1TXD1
UART1_RX_DATARXD1RXD1RXD1
UART1_CTS_BPIO18 (Bank=0,Bit=18)RTS1RTS1 (TxEn)
UART1_RTS_BPIO19 (Bank=0,Bit=19)CTS1PIO19


UART2
group
UART2UART2 + RTS/CTSUART2 + RS485I2C4SPI3 masterSPI3 slaveCAN2UART2 + CAN2I2C4 + CAN2GPIO
UART2_TX_DATATXD2TXD2TXD2I2CCLK4PIO200CS3PIO20TXD2I2CCLK4PIO20 (Bank=0,Bit=20)
UART2_RX_DATARXD2RXD2RXD2I2CDTA4SCLK3SCLK3PIO21RXD2I2CDTA4PIO21 (Bank=0,Bit=21)
UART2_CTS_BPIO22RTS2RTS2 (TxEn)PIO22MOSI3MOSI3CAN2TXDCAN2TXDCAN2TXDPIO22 (Bank=0,Bit=22)
UART2_RTS_BPIO23CTS2PIO23PIO23MISO3MISO3CAN2RXDCAN2RXDCAN2RXDPIO23 (Bank=0,Bit=23)


UART3
group
UART3UART3 + RTS/CTSUART3 + RS485UART3 + CAN1CAN1GPIO
UART3_TX_DATATXD3TXD3TXD3TXD3PIO24PIO24 (Bank=0,Bit=24)
UART3_RX_DATARXD3RXD3RXD3RXD3PIO25PIO25 (Bank=0,Bit=25)
UART3_CTS_BPIO26RTS3RTS3 (TxEn)CAN1TXDCAN1TXDPIO26 (Bank=0,Bit=26)
UART3_RTS_BPIO27CTS3PIO27CAN1RXDCAN1RXDPIO27 (Bank=0,Bit=27)


UART5
group
UART5UART5 + RTS/CTSUART5 + RS485SPI2 masterSPI2 slaveGPIO
CSI_DATA00TXD5TXD5TXD5SCLK2SCLK2PIO117 (Bank=3,Bit=21)
CSI_DATA01RXD5RXD5RXD5PIO1180CS2PIO118 (Bank=3,Bit=22)
CSI_DATA02PIO119CTS5PIO119MOSI2MOSI2PIO119 (Bank=3,Bit=23)
CSI_DATA03PIO120RTS5RTS5 (TxEn)MISO2MISO2PIO120 (Bank=3,Bit=24)


UART6
group
UART6, PWMUART6 + RTS/CTSUART6 + RS485I2C1, PWMI2C2I2C1 + I2C2GPIO, PWM
CSI_MCLKTXD6TXD6TXD6I2CDTA1PIO113I2CDTA1PIO113 (Bank=3,Bit=17)
CSI_PIXCLKRXD6RXD6RXD6I2CCLK1PIO114I2CCLK1PIO114 (Bank=3,Bit=18)
CSI_VSYNCPIO115 / PWM7CTS6PIO115 / PWM7PIO115 / PWM7I2CDTA2I2CDTA2PIO115 (Bank=3,Bit=19) / PWM7
CSI_HSYNCPIO116 / PWM8RTS6RTS6 (TxEn)PIO116 / PWM8I2CCLK2I2CCLK2PIO116 (Bank=3,Bit=20) / PWM8


UART7
group
UART7UART7 + RTS/CTSUART7 + RS485LCDGPIO
LCD_DATA16TXD7TXD7TXD7LCD_DATA16PIO85 (Bank=2,Bit=21)
LCD_DATA17RXD7RXD7RXD7LCD_DATA17PIO86 (Bank=2,Bit=22)
LCD_DATA07PIO76CTS7PIO76LCD_DATA07PIO76 (Bank=2,Bit=12)
LCD_DATA06PIO75RTS7RTS7 (TxEn)LCD_DATA06PIO75 (Bank=2,Bit=11)

UART8
group
UART8UART8 + RTS/CTSUART8 + RS485LCDGPIO
LCD_DATA20TXD8TXD8TXD8LCD_DATA20PIO89 (Bank=2,Bit=25)
LCD_DATA21RXD8RXD8RXD8LCD_DATA21PIO90 (Bank=2,Bit=26)
LCD_DATA05PIO74CTS8PIO74LCD_DATA05PIO74 (Bank=2,Bit=10)
LCD_DATA04PIO73RTS8RTS8 (TxEn)LCD_DATA04PIO73 (Bank=2,Bit=9)


SPI1
group
SPI1 masterSPI1 slaveGPIO
CSI_DATA04SCLK1SCLK1PIO121 (Bank=3,Bit=25)
CSI_DATA06MOSI1MOSI1PIO123 (Bank=3,Bit=27)
CSI_DATA07MISO1MISO1PIO124 (Bank=3,Bit=28)

Note: The SPI chip select in slave mode is in SDIO1 group. The SDIO1 interface must be disabled to use the SPI slave mode with the SPI1 interface, see SDIOx_ENABLE.


GPIO, LCD
group
LCDGPIO, PWM, ADC
GPIO1_IO03PIO3PIO3 (Bank=0,Bit=3) / AIN3
GPIO1_IO08PIO8PIO8 (Bank=0,Bit=8) / PWM1 / AIN8
UART5_TX_DATAPIO30PIO30 (Bank=0,Bit=30)
UART5_RX_DATAPIO31PIO31 (Bank=0,Bit=31)
LCD_CLKLCD_CLKPIO64 (Bank=2,Bit=0)
LCD_ENABLELCD_ENABLEPIO65 (Bank=2,Bit=1)
LCD_HSYNCLCD_HSYNCPIO66 (Bank=2,Bit=2)
LCD_VSYNCLCD_VSYNCPIO67 (Bank=2,Bit=3)
LCD_RESETLCD_RESETPIO68 (Bank=2,Bit=4)
LCD_DATA00LCD_DATA00PIO69 (Bank=2,Bit=5)
LCD_DATA01LCD_DATA01PIO70 (Bank=2,Bit=6)
LCD_DATA02LCD_DATA02PIO71 (Bank=2,Bit=7)
LCD_DATA03LCD_DATA03PIO72 (Bank=2,Bit=8)
LCD_DATA04LCD_DATA04PIO73 (Bank=2,Bit=9)
LCD_DATA05LCD_DATA05PIO74 (Bank=2,Bit=10)
LCD_DATA06LCD_DATA06PIO75 (Bank=2,Bit=11)
LCD_DATA07LCD_DATA07PIO76 (Bank=2,Bit=12)
LCD_DATA08LCD_DATA08PIO77 (Bank=2,Bit=13)
LCD_DATA09LCD_DATA09PIO78 (Bank=2,Bit=14)
LCD_DATA10LCD_DATA10PIO79 (Bank=2,Bit=15)
LCD_DATA11LCD_DATA11PIO80 (Bank=2,Bit=16)
LCD_DATA12LCD_DATA12PIO81 (Bank=2,Bit=17)
LCD_DATA13LCD_DATA13PIO82 (Bank=2,Bit=18)
LCD_DATA14LCD_DATA14PIO83 (Bank=2,Bit=19)
LCD_DATA15LCD_DATA15PIO84 (Bank=2,Bit=20)
LCD_DATA16LCD_DATA16PIO85 (Bank=2,Bit=21)
LCD_DATA17LCD_DATA17PIO86 (Bank=2,Bit=22)
LCD_DATA18LCD_DATA18PIO87 (Bank=2,Bit=23) / PWM5
LCD_DATA19LCD_DATA19PIO88 (Bank=2,Bit=24)
LCD_DATA20LCD_DATA20PIO89 (Bank=2,Bit=25)
LCD_DATA21LCD_DATA21PIO90 (Bank=2,Bit=26)
LCD_DATA22LCD_DATA22PIO91 (Bank=2,Bit=27)
LCD_DATA23LCD_DATA23PIO92 (Bank=2,Bit=28)
SNVS_TAMPER0PIO128PIO128 (Bank=4,Bit=0)
SNVS_TAMPER1PIO129PIO129 (Bank=4,Bit=1)
SNVS_TAMPER2PIO130PIO130 (Bank=4,Bit=2)
SNVS_TAMPER3PIO131PIO131 (Bank=4,Bit=3)
SNVS_TAMPER4PIO132PIO132 (Bank=4,Bit=4)
SNVS_TAMPER5PIO133PIO133 (Bank=4,Bit=5)
SNVS_TAMPER6PIO134PIO134 (Bank=4,Bit=6)
SNVS_TAMPER7PIO135PIO135 (Bank=4,Bit=7)

All interface groups here come up as GPIO keepers after boot, except the UART1 interface. This interface is set up as UART1 (RXD1/TXD1 only), because it is used by the Bootloader for the Chiptool serial protocol. It's also the standard interface for the RTOS shell by default.
The appropriate pin functionality will be activated when the corresponding API function is called to initialize the interface, e.g. fossil_initmode(), fossil_set_flowcontrol(), fossil_set_rs485(), spiInit(), canInit(), i2cInit(), pwmEnable().

Note: The SPI slave mode must be selected via the CHIP.INI SPIx_SLAVE entry.


Ethernet, USB interfaces

The Ethernet and USB interfaces are only usable in their Ethernet and USB functionality. Other pin functions are not supported on these pins by the @CHIP-RTOS-LNX.

If the USB1 interface is used, then the pins of this interface must be connected as USB OTG, since this interface is specified as an USB OTG type in the kernel device tree.
Note: The @CHIP-RTOS-LNX currently does not provide any USB device mode functionality, even though the hardware interface must be setup as OTG.

If the USB2 interface is used, then the pins of this interface must be connected as USB host, since this interface is specified as an USB host type in the kernel device tree.






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