IPC@CHIP® RTOS-LNX – API Documentation

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CHIP.INI [SDIO]


[SDIO]
SDIOx_ENABLE=0/1

Enables the usage of the IPC@CHIP®'s SDIO interface. Set to 0 to disable the SDIO interface. In this case the dedicated pins can be used as GPIOs.
Default:
By default, the SDIO interfaces are enabled.
Example:
[SDIO]
SDIO1_ENABLE=1
SDIO2_ENABLE=0
Since
V1.06
Only supported at @CHIP-RTOS-LNX target(s)
SC1x5


[SDIO]
SDIOx_MAXCLK=Max. clock frequency in Hz

Set the maximum allowed clock frequency for this SDIO interface in Hz. Set to 0 for no clock frequency limit.
Default:
By default, the SDIO clock frequency is not limited.
Example:
[SDIO]
SDIO1_MAXCLK=0
SDIO2_MAXCLK=25000000
Since
V1.06
Only supported at @CHIP-RTOS-LNX target(s)
SC1x5


[SDIO]
SDIO1_1V8=0/1

Select whether the SDIO interface has a voltage select for 1.8V or not. Set to 1 if the SDIO interface has a voltage select.
Default:
No voltage select (0) is the default setting.
Example:
[SDIO]
SDIO1_1V8=1
Since
V1.06
Only supported at @CHIP-RTOS-LNX target(s)
SC1x5


[SDIO]
SDIO1_WP=0/1

Select whether the SDIO interface has a write-protect signal or not. Set to 0 if the SDIO interface has no write-protect signal.
Default:
A write-protect signal (1) is assumed by default.
Example:
[SDIO]
SDIO1_WP=0
Since
V1.21
Only supported at @CHIP-RTOS-LNX target(s)
SC1x5





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